1. Field of the Invention
The invention relates to electronic imaging technology and, more particularly, to a technique that ameliorates the effects of row-wise and column-wise coherent noise in Active-Pixel Sensor (APS) imaging systems.
2. Description of the Related Art
Since the 1970s, charge-coupled devices (CCDs) have been used in the majority conventional imaging circuits, serving as a mechanism for converting a pixel of light energy into an electrical signal that represents the intensity of light energy. In general, CCDs utilize a photogate to convert light energy into an electrical charge. A series of electrodes transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, including a high sensitivity and fill factor, CCDs also suffer from a number of drawbacks. Notable among these drawbacks, which also include limited readout rates and dynamic range limitations, is the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, more recently developed imaging circuits use active pixel sensor (APS) cells to convert a pixel of light energy into an electrical signal. With APS cells, a conventional photodiode is typically combined with a number of active transistors that, in addition to forming an electrical signal, perform attendant functions such as amplification, readout control, and reset control.
A more or less canonical implementation of an APS cell is illustrated in FIG. 1. The APS cell may be seen there to include a photodiode 10, a Row Select Transistor (RST) 11, and a charge, or current, sensing amplifier 12. RST 11 has a gate electrode 111 coupled to a RST input signal, a (drain/source) electrode 112 coupled to a supply voltage VDD, and a (source/drain) electrode 113 coupled to cathode 101 of photodiode 10. Anode 102 of the photodiode is grounded. The cathode of photodiode 12 is coupled to input 121 of amplifier 12. The output of the pixel cell appears at output 122 of amplifier 12. The operation of an APS cell, such as illustrated in FIG. 1, is well understood by artisans of ordinary skill and, hence, for the sake of brevity, will not be narrated here.
APS cells are often fabricated using CMOS processing technology, which enables the integration of an amplifier at each pixel site and in this manner eliminates the bus capacitance and bus resistance problems associated with predecessor technologies. Whereas at one time the transistors used for manufacturing CMOS APS cells occupied a substantial portion of the pixel, transistor sizes are now small enough to allow light to penetrate a substantial portion of the pixels. The advent of submicron photolithography has played a significant role in stimulating the deployment of APS imagers. However, because the readout circuitry of the APS continues to consume a disproportionate area on the pixel cell, more improvements are anticipated in order to increase the sensitivity of the device and thereby render APS technology competitive in high-performance applications.
CMOS imagers sense light in largely the same way as CCDs. Both technologies convert incident light (photons) into electronic charge (electrons) by the same photo-conversion process. Color sensors can be constructed in substantially the same way with both technologies: normally by coating each individual pixel with a colorized filter. However, other operational aspects are markedly disparate. In APS systems, charge packets are not transferred, they are instead detected as early as possible by charge sensing amplifiers, which are made from CMOS transistors.
CMOS imaging technologies are based on the either of two embodiments of photo element: the photogate and the photodiode. Generally, photodiode sensors are more sensitive, especially to blue light, which can be important at the top of each column of pixels. The passive pixels contain just one transistor, which is used as a charge gate, switching the contents of the pixel to the charge amplifiers. These “passive pixel” CMOS sensors operate much like analog DRAMs. In active CMOS sensors, amplifiers are implemented in each pixel. Active pixel CMOS sensors usually contain at least three transistors per pixel. As might be expected, APS cells are characterized by lower noise but poorer packing density than passive pixel CMOS.
Because CMOS APS cells can be manufactured on conventional CMOS production lines, they offer the potential for significantly lower cost and also suggest the capability to be integrated with other functions, such as timing logic and analog-to-digital conversion (ADC). The promised benefits of the technology include lower power, random readout, and the realization of on-chip ADC and timing functions. The CMOS process allows the integration of an amplifier at each site. More importantly, APS cells, in theory, are able to utilize the high level of CMOS integration that can enable the fabrication of an imaging system or camera on a chip, rather than a mere imager.
Nevertheless, deployment of APS technology has been hindered by the inherently higher noise of the APS sensors (due to the readout structure), the lower quantum efficiency (due to the lower fill factor), and the compromises in semiconductor manufacturing that must be made to incorporate multiple features on a single semiconductor die.
In addition, one of the salutary features of APS imaging arrays, convenience of addressability, is burdened by an operational side effect. Specifically, a conventional APS system consists essentially of a two-dimensional array of the pixel cells, arranged in rows and columns. Rows in the array are addressed sequentially. But the row-wise addressing scheme may introduce row-wise coherent noise in output images. In other architectures, column-wise coherent noise is prevalent. The coherency of noise exacerbates its perceptibility to a human eye and therefore renders coherent noise especially objectionable.
Accordingly, what is desired is an APS system that mitigates the effects of row-wise, or column-wise, coherent noise that is associated with the addressing of an APS array. Because pixel architecture considerations impel a preference to reserve the greater proportion of pixel area to the photodetector (photodiode or photogate), favored approaches should be simple and not consume a disproportionate degree of pixel real estate. In addition, the approach should not be susceptible to the generally deleterious effect of mismatch among the active devices that are required to form the APS array.